Engineering
Technical Writing
Notes on RTL design, FPGA systems, embedded pipelines, and the engineering problems worth writing about.
Heterogeneous CDC Arbiters (Part 2): Architecting the Synchronization Matrix
Resolving metastability across multiple clock domains requires a scalable RTL architecture. Discover how to build parameterized synchronization matrices in Verilog using generate blocks, and explore the delicate balance between clock frequency, multi-cycle latency penalties, and MTBF.
Jul 11, 2026
Heterogeneous CDC Arbiters (Part 1): The Spatial Contention Problem
In a perfectly synchronous FPGA, managing shared resources is easy. But in the real world, your fast processors and slow peripherals run on entirely independent clocks. If you wire their requests directly to a shared SRAM bus, you are mathematically guaranteeing a catastrophic hardware collision. Here is how we fix it.
Jun 30, 2026
Digital Verification: Simulating the Analog World
You cannot pipe an analog waveform into a digital simulator. Discover how to bridge the verification gap using Python data generation, Verilog's $readmemh, and self-checking testbenches to prove your mixed-signal RTL works before you ever touch a physical FPGA.
Jun 27, 2026
AXI4-Stream: The Language of Data Movement
Raw data routing is a recipe for disaster in dynamic FPGA systems. If you wire modules together without a protocol, fast upstream logic will constantly overwrite slow downstream processors. Enter AXI4-Stream: the industry-standard language of data movement.
Jun 23, 2026
Clock Domain Crossing (CDC): The Art of Avoiding Metastability
FPGAs thrive on parallel processing, but moving data between asynchronous clock domains introduces a silent, catastrophic threat: metastability. Discover the physics behind timing violations, the dangers of multi-bit data tearing, and how to safely bridge clock boundaries using Gray-coded Asynchronous FIFOs.
Jun 22, 2026
Heterogeneous CDC Arbiters (Part 2): Architecting the Synchronization Matrix
Resolving metastability across multiple clock domains requires a scalable RTL architecture. Discover how to build parameterized synchronization matrices in Verilog using generate blocks, and explore the delicate balance between clock frequency, multi-cycle latency penalties, and MTBF.
Jul 11, 2026
Heterogeneous CDC Arbiters (Part 1): The Spatial Contention Problem
In a perfectly synchronous FPGA, managing shared resources is easy. But in the real world, your fast processors and slow peripherals run on entirely independent clocks. If you wire their requests directly to a shared SRAM bus, you are mathematically guaranteeing a catastrophic hardware collision. Here is how we fix it.
Jun 30, 2026
Digital Verification: Simulating the Analog World
You cannot pipe an analog waveform into a digital simulator. Discover how to bridge the verification gap using Python data generation, Verilog's $readmemh, and self-checking testbenches to prove your mixed-signal RTL works before you ever touch a physical FPGA.
Jun 27, 2026
AXI4-Stream: The Language of Data Movement
Raw data routing is a recipe for disaster in dynamic FPGA systems. If you wire modules together without a protocol, fast upstream logic will constantly overwrite slow downstream processors. Enter AXI4-Stream: the industry-standard language of data movement.
Jun 23, 2026
Clock Domain Crossing (CDC): The Art of Avoiding Metastability
FPGAs thrive on parallel processing, but moving data between asynchronous clock domains introduces a silent, catastrophic threat: metastability. Discover the physics behind timing violations, the dangers of multi-bit data tearing, and how to safely bridge clock boundaries using Gray-coded Asynchronous FIFOs.
Jun 22, 2026
Bridging the Divide: Why FPGAs Need ADCs to Read the Real World
FPGAs cannot directly process analog signals, so an ADC is essential to convert continuous voltages into digital data that the FPGA can handle; proper analog front‑end filtering prevents aliasing, and the FPGA’s deterministic timing enables precise, high‑speed sampling and reliable data transfer via custom SPI and FIFO architectures.
Jun 18, 2026