Heterogeneous CDC Arbiters (Part 1): The Spatial Contention Problem

If you have built a linear RTL pipeline like an ADC streaming data into a DSP filter and out to a UART you are used to data moving in one direction. But as your FPGA architectures scale in complexity, you will inevitably hit a wall: you will need to share resources.

Imagine a system with a fast soft-core processor, a dedicated math co-processor, and a slow peripheral controller. All three of these masters need to read and write to the same block of Block RAM (BRAM). If they all try to drive the memory bus at the exact same time, your data is corrupted.

You need a traffic cop. You need an Arbiter.

The Simple (But Flawed) Solution

In a perfectly synchronous world where all three masters operate on the exact same clock, arbitration is trivial. You write a combinatorial Priority Encoder. If Master A asserts a request, it gets the bus. If Master B requests it, it only gets the bus if Master A is quiet.

// A standard, strictly synchronous priority encoder
always @(*) begin
    grant_a = 1'b0; grant_b = 1'b0;
    if (req_a)      grant_a = 1'b1;
    else if (req_b) grant_b = 1'b1;
end

This works beautifully until you introduce the reality of modern FPGA design: Heterogeneous Clocks.

The Asynchronous Boundary

In a high-performance system, forcing every master to run on the same clock is incredibly inefficient. A fast RISC-V core might run at 200 MHz, while a slow I2C controller runs at 10 MHz. To maximize performance, we decouple them. Every master runs on its own independent clock domain.

But our shared resource and therefore our Arbiter must run on its own specific clock (CLK_ARB).

This creates a massive architectural hazard. Master A's request (req_a) is generated on a 200 MHz clock. Master B's request (req_b) is generated on a 10 MHz clock. Both of these request lines are crossing an asynchronous boundary into the Arbiter's domain.

The Threat of Combinatorial Metastability

What happens if you route these raw, asynchronous request lines directly into a standard priority encoder?

Because the master clocks are completely unaligned with CLK_ARB, it is mathematically guaranteed that eventually, a master will assert its request at the exact picosecond the Arbiter's clock is rising.

This violates the setup and hold time of the Arbiter's internal flip-flops. The logic goes metastable. The Arbiter's transistors cannot decide if the request is a 1 or a 0. As shown in Panel 3 of the guide above, the output Grant line begins to oscillate wildly, potentially granting the shared bus to both masters simultaneously, causing a catastrophic hardware collision that permanently corrupts the SRAM.

The Architectural Fix: Synchronization Matrices

To solve the spatial contention problem safely, we cannot just evaluate the requests; we must capture and stabilize them first.

Before a request ever touches the combinatorial arbitration logic, it must pass through a dedicated synchronization matrix (typically a parallel bank of 2-FF synchronizers) clocked by CLK_ARB.

Look at Panel 4 in the visual guide. When a raw request hits the first stage of the synchronizer, that register might go metastable. But because we chained a second register behind it, the signal has an entire clock cycle to settle out of its chaotic state into a clean logic level. Only when the asynchronous requests are safely pulled into the Arbiter's time domain and proven stable can we evaluate who wins the bus.

In Part 2, we will break down the exact RTL required to build this parallel synchronizer matrix, and how to minimize the multi-cycle latency penalty it introduces.

In the meantime, if you want to see the complete, synthesis-ready Verilog for a multi-master asynchronous arbiter, you can check out the architecture on my GitHub here: 🔗 Heterogeneous CDC Arbiter Repository