Jehkaran Singh
B.Tech Electronics & Computer Engineering · UPES Dehradun · CGPA 8.7
RTL Design · Digital Verification · FPGA Systems
About
An inquisitive learner who observes too closely when it comes to systems — any system. Prior diploma in Electronics Engineering Technology from Seneca College, Canada. Targeting VLSI and semiconductor roles specialising RTL, and Physical design FPGA design engineering.
Skills
Hardware & HDL
SoC & Verification
Embedded & Firmware
EDA & Tools
Projects
MINERVA P1 — CDC Heterogeneous FIFO Arbiter & Timestamp Engine
CompleteClock-domain-crossing arbitration engine in SystemVerilog featuring a round-robin arbiter, heterogeneous FIFO depth management, and per-channel timestamp tagging. Synthesized on Xilinx XC7Z020 (321 LUTs, 365 FFs, 4× RAMB36). Hardware-verified via UART on Zedboard using Vivado 2025.1.
MINERVA P2 — 5-Stage Pipelined RV32I CPU
Complete32-bit RISC-V CPU in SystemVerilog with a classic 5-stage pipeline (IF/ID/EX/MEM/WB), full data hazard forwarding (EX-EX, MEM-EX), load-use stall detection, and branch flush. Hardware-verified on Zedboard running bubble sort with sorted output confirmed over UART.
MINERVA P3 — Cache Controller & DMA Engine
In ProgressDirect-mapped cache controller with hit/miss handling and a scatter-gather DMA engine. Sits between the P2 RISC-V CPU and a slower backing memory. AXI4 master interface, configurable burst length, interrupt-driven completion.
MINERVA P4 — AXI Crossbar Interconnect
In ProgressParameterizable AXI crossbar connecting the RISC-V CPU, cache controller, DMA engine, and peripherals. Multi-master multi-slave arbitration with address decoding and full AXI4 handshake compliance.
MINERVA P5 — Fault Injection Framework & OpenLane Tapeout
In ProgressHardware fault injection framework targeting pipeline registers of the P2 RISC-V CPU. Single-event upset simulation with error detection and correction circuits. Full RTL-to-GDS flow through OpenLane on the SKY130 PDK.
AXI-Lite Hardware Accelerator with Firmware Control
CompleteAXI-Lite slave with register file, control FSM, and datapath. Synthesized in Vivado, verified via directed testbenches, driven by bare-metal firmware on FPGA. MMIO address decode; FSM: IDLE→EXEC→DONE; firmware polls status register for completion.
Multichannel Signal Processing System
In Progress3-channel round-robin SPI ADC pipeline with per-channel AXI-Lite accelerators for FIR filtering. On-fabric DSP algorithms for edge computing without host dependency. Arch: Arbitrated SPI master → dedicated FIR blocks → central DSP core via AXI-Lite fabric.
FPGA-Based Optical Sensor Acquisition System
CompleteMixed-signal FPGA pipeline: SPI ADC master, synchronous FIFO, UART TX in Verilog RTL. Deterministic 1 kHz streaming. 16-deep FIFO decouples acquisition/UART domains. CDC via gray-coded pointers, verified with ModelSim directed testbench.
Certifications
- ISWDP Samsung / IISc / Synopsys SARA
- Control Systems Fundamentals — Siemens
- ERP Systems Training — Shoppers Drug Mart
Technical Writing
Links