Jehkaran Singh
B.Tech Electronics & Computer Engineering · UPES Dehradun · CGPA 8.7
RTL Design · Digital Verification · FPGA Systems
About
An inquisitive learner who observes too closely when it comes to systems — any system. Prior diploma in Electronics Engineering Technology from Seneca College, Canada. Targeting VLSI and semiconductor roles specialising RTL, and Physical design FPGA design engineering.
Skills
Hardware & HDL
SoC & Verification
Embedded & Firmware
EDA & Tools
Projects
RISC-V CPU with Custom AES ISA Extension
In ProgressPipelined RV32I in Verilog with a custom AES instruction — SubBytes/ShiftRows/MixColumns datapath in the execute stage. 5-stage pipeline with hazard detection and forwarding unit. AES in R-type format with dedicated combinational crypto datapath bypassing the ALU. UART plaintext-to-ciphertext demo on FPGA.
AXI-Lite Hardware Accelerator with Firmware Control
CompleteAXI-Lite slave with register file, control FSM, and datapath. Synthesized in Vivado, verified via directed testbenches, driven by bare-metal firmware on FPGA. MMIO address decode; FSM: IDLE→EXEC→DONE; firmware polls status register for completion.
Multichannel Signal Processing System
In Progress3-channel round-robin SPI ADC pipeline with per-channel AXI-Lite accelerators for FIR filtering. On-fabric DSP algorithms for edge computing without host dependency. Arch: Arbitrated SPI master → dedicated FIR blocks → central DSP core via AXI-Lite fabric.
FPGA-Based Optical Sensor Acquisition System
CompleteMixed-signal FPGA pipeline: SPI ADC master, synchronous FIFO, UART TX in Verilog RTL. Deterministic 1 kHz streaming. 16-deep FIFO decouples acquisition/UART domains. CDC via gray-coded pointers, verified with ModelSim directed testbench.
Certifications
- ISWDP Samsung / IISc / Synopsys SARA
- Control Systems Fundamentals — Siemens
- ERP Systems Training — Shoppers Drug Mart
Links