Hardware & Software

Projects

RTL design, FPGA systems, and embedded pipelines. All projects are open source.

Multichannel FPGA Signal Acquisition System

Complete

Full RTL pipeline on Zedboard: MCP3204 SPI ADC → channel mux FSM → per-channel FIR filtering → UART framer → packet FIFO → UART TX. Python monitor and MATLAB analysis on the PC side.

RISC-V CPU with AES ISA Extension

Complete

Custom RISC-V core with extended instruction set for AES operations. Designed for hardware-accelerated cryptographic workloads.

AXI-Lite Hardware Accelerator

Complete

AXI-Lite compliant hardware accelerator with C firmware driver. UVM testbench for verification. Cadence Innovus PnR on FreePDK45.

Elevator FSM — FCFS vs SSTF

Complete

RTL implementation comparing First Come First Served and Shortest Seek Time First scheduling algorithms for elevator control.

CMOS Bandgap Reference

Complete

Temperature-independent voltage reference circuit using bipolar junction transistors in CMOS process.

Scatter-Gather DMA Engine

In Progress

High-throughput DMA engine with scatter-gather capability. AXI4 master interface, configurable burst length, interrupt-driven completion.